1. Field of the Invention
The present invention relates to a silicon wafer to be used for production of semiconductor devices. More particularly, the present invention relates to a silicon wafer composed of a surface layer and an internal layer, the former for active device region having high-quality crystallinity and high stress resistance, and the latter being highly capable of gettering metal contaminants.
2. Description of the Related Art
Semiconductor devices remarkably advancing in integration, performance, and function need a finer design rule, say 65-45 nm, than before for their elements or constituents. Such semiconductor devices are formed on a substrate which is a silicon water produced by crystal pulling method such as Czochralski method (CZ) or magnetic field applied Czochralski method (MCZ).
Silicon wafers need the gettering of metal contaminants in trace amounts coming into them during device fabrication so that devices have improved yields and reliability. Therefore, it is highly necessary for them to have the active region for devices which is limited in aggregates of point detects, such as lattice vacancies, and precipitates of interstitial oxygen, such as bulk micro defects (BMD). The aggregates of point detects include crystal originated particles (COP) and laser scattering tomography defects (LSTD). BMD denotes minute amorphous silicon oxide in octahedral form.
A conventional way of gettering metal contaminants is by extrinsic gettering method (EG), which permits metal contaminants to be captured by a backside damage layer, backside polysilicon layer, or phosphorus impurity diffusion layer. A new way of gettering metal contaminants is by intrinsic gettering method (IG), which employs a gettering site formed in the bulk of the silicon wafer. Now, this IG method is popular for production of semiconductor devices.
The IG method for the silicon wafer prepared by CZ or MCZ method includes heat treatment that causes supersaturated interstitial oxygen remaining in the silicon wafer to separate out, thereby forming BMD in the bulk of the silicon wafer, inducing secondary dislocations and stacking faults around them, and utilizing the precipitates and their surrounding as the gettering site for metal contaminants. This method requires that the occurrence of BMD be prevented in the surface layer as the device active region.
There have been proposed several methods for preparing silicon wafers with IG effect. These methods involve heat treatment that controls precipitation of supersaturated interstitial oxygen, adjusts precipitating nuclei, dissolution of precipitates and precipitating nuclei, and diffusion of interstitial oxygen. High-temperature heat treatment at 1100 to 1300° C., for example, causes precipitating nuclei to diminish or disappear. Such heat treatment also causes oxygen to diffuse outward from the surface layer of the silicon wafer, thereby forming the denuded zone (DZ), which is a defect-free layer containing a very small amount of BMD in the device active region. Low-temperature heat treatment at 500-900° C., for example, forms precipitating nuclei which are uniform in size and density. Middle-temperature heat treatment at about 1000° C., for example, controls the growth of BMD and secondary defects or controls the dissolution of certain precipitates.
The phenomenon of BMD formation is regarded as equivalent to condensation of supersaturated gas into liquid drops. It may be discussed in terms of condensation of supersaturated oxygen in a silicon wafer according to thermal equilibrium based on statistical thermodynamics, which will be briefly mentioned below. Condensation of supersaturated oxygen may be regarded as proceeding in such a way that Helmholtz free energy becomes minimal in the thermal system. Helmholtz free energy in the thermal system may be regarded approximately as the sum of free energy of BMD and free energy of oxygen dissolving in a silicon wafer. The free energy of BMD includes its internal energy, surface energy, stress field energy, electric field energy, and temperature-entropy product. Here, entropy is obtained from the quantity of state involved in the distribution of thermal energies. The free energy may also be derived from the partition function of thermal canonical distribution.
Elucidation of BMD formation reveals that the free energy of BMD depends on the diameter of BMD and there exists a critical nucleus diameter for which the free energy of BMD becomes maximal. BMD smaller than the crystal nucleus diameter at a certain temperature dissolves to diminish or disappear. However, BMD grows in the opposite case, so that the thermal system takes on a minimal free energy. Here, the critical nucleus diameter increases in proportion to the temperature of heat treatment, and it depends on the degree of supersaturation of oxygen.
It is considered that BMD formation makes oxygen clusters in a silicon wafer uniform nuclei. Other impurities such as nitrogen (N) and carbon (C), which lower the free energy of BMD, and lattice vacancies also function as precipitating nuclei. Moreover, p-type or n-type impurities in a silicon wafer become activated to create the electric field energy, thereby affecting oxygen precipitation. Thus, one way to prepare a silicon wafer having the IG effect mentioned above is by adding such impurities as N and C or by controlling the freezing of lattice vacancies during heat treatment. There has also been proposed a method of controlling the rate of heating up to the heat treatment temperature or the rate of cooling from the heat treatment temperature in considering that the critical nucleus diameter of BMD increases at a rate that depends on temperature and in considering the substantial growth rate of BMD. Some of these methods are in practical use.
Among the above-mentioned methods for preparing silicon wafers having the IG effect is the one which is intended to form adequate BMD in the bulk of a silicon wafer and to disappear aggregates of lattice vacancies as grown-in defects in the DZ layer mentioned above, thereby improving the quality of the silicon wafer. (See Japanese Patent No. 3171308.) This method is characterized in that the high-temperature heat treatment is carried out in a reducing gas, such as hydrogen (H2), or an inert gas, such as argon, which removes the oxide layer (SiOx layer) that occurs on the inside wall of the cavity of the aggregates, thereby effectively disappearing aggregates. The silicon wafer prepared in this manner will be referred to as anneal wafer hereinafter.
According to another method proposed so far, the silicon wafer is processed in such a way that it permits adequate BMD to form in its bulk and it undergoes silicon epitaxial growth, so that the silicon epitaxial layer with good crystallinity is used as the device active region. (See Japanese Patent Laid-open No. 2006-188423.) The silicon wafer prepared by this method will be referred to as an epitaxial wafer with IG treatment.
In the meantime, the microstructure of semiconductor elements intended for high integration, high performance, and high function increases stress in the surface layer of a silicon wafer. Typical of such stresses are one that occurs around the fine pattern constituting MISFET and one that is accompanied by residual stress resulting from ion implantation with n-type or p-type impurity. (See IEEE Transaction on Semiconductor Manufacturing, February 2005, vol. 18, No. 1, p. 19-25.)
The manufacturing process for such devices tends toward temperature reduction and time saving. For example, it has become common to carry out heat treatment in the diffusion furnace at a temperature lower than 1000° C. Another example of temperature reduction is replacement of rapid thermal annealing (RTA), which has been common in thermal process in fabrication of semiconductor devices, by low thermal budget heat treatment such as flash lamp annealing and laser spike annealing. Incidentally, RTA is annealing by irradiation with halogen lamp rays, which lasts for several seconds to ten-odds seconds. By contrast, the low thermal budget mentioned above merely takes a very short time, say a few milliseconds. Such device fabrication process involves difficulties in relieving by heat treatment the stresses which increase as the semiconductor elements become finer. Moreover, heat treatment by low thermal budget with rapid temperature rise and fall causes thermal stress to increase in the surface layer of a silicon wafer.
The recent trend in semiconductor devices and fabrication process mentioned above results in the anneal wafer and epitaxial wafer with IG treatment inevitably decreasing in the concentration of dissolved oxygen in the surface layer of the wafer. This situation leads to defects such as dislocation due to increased stresses in the surface layer of the wafer, and these defects easily propagate. Thus, anneal wafers and epitaxial wafers with IG treatment are suffering the disadvantage that the yield of semiconductor devices decreases due to increased stresses in the surface layer of the wafer. The device fabrication process that is performed at a lower temperature in a shorter time does not compensate for dissolved oxygen in the surface layer of the wafer during device fabrication. This problem is encountered also by silicon epitaxial wafers without IG treatment.
In order to cope with the finer device structure, which increases stresses in the surface layer of the wafer, and the device fabrication process, which is performed at a lower temperature in a shorter time, there has arisen a demand for a silicon wafer which permits an adequate amount of oxygen to dissolve in the surface layer of the wafer before the wafer passes through the device fabrication process and which prevents the occurrence of dislocations and is capable of pinning dislocations.